Figure 2. Abstract diagrams for seesaw gate circuits. (*a*) The general form of a gate node. Each gate *i* may be connected to many wires on each side, potentially all *N* nodes in the network, including itself. For each wire from the right side of gate *i* to the left side of gate *j*, the initial concentration of the free signal *w*_{i,j} may be written above the wire, and the initial concentrations of gate complex *g*_{j,i:i} (*w*_{j,i} bound to gate *i*) and *g*_{i:i,j} (*w*_{i,j} bound to gate *i*) may be written within the node at the ends of the corresponding wires. Gate concentrations are simply omitted if they are zero. Initial concentrations of *th*_{j,i:i} (the threshold for *w*_{j,i} arriving at gate *i*) and *th*_{i:i,j} (the threshold for *w*_{i,j} arriving at gate *i*) may be written in the same locations as *g*_{j,i:i} and *g*_{i:i,j}, respectively, but as negative numbers—or omitted if they are zero. (*b*) The general form of a wire. Each wire is specifically connected on its left end to the right side of a gate node, and connected on its right end to the left side of a gate node. (*c*) An example circuit with five realized gates (numbered circles), five virtual gates (numbers at ends of wires), and 11 wires. Each wire is identified by the two gates it connects; thus the virtual gates serve to provide full names (and sequences) to their incident wires. Note that circuit diagrams may be drawn without providing gate numbers, as they are not relevant to circuit function.